Design and Implementation of Multiplexed and Obfuscated Physical Unclonable Function

Model building attack on Physical Unclonable Functions (PUFs) by using machine learning (ML) techniques has been a focus in the PUF research area. PUF is a hardware security primitive which can extract unique hardware characteristics (i.e., device-specific) by exploiting the intrinsic manufacturing process variations during integrated circuit (IC) fabrication. The nature of the manufacturing process variations which is random and complex makes a PUF realistically and physically impossible to clone atom-by-atom. Nevertheless, its function is vulnerable to model-building attacks by using ML techniques. Arbiter-PUF is one of the earliest proposed delay-based PUFs which is vulnerable to ML-attack. In the past, several techniques have been proposed to increase its resiliency, but often has to sacrifice the reproducibility of the Arbiter-PUF response. In this paper, we propose a new derivative of Arbiter-PUF which is called Mixed Arbiter-PUF (MA-PUF). Four Arbiter-PUFs are combined and their outputs are multiplexed to generate the final response. We show that MA-PUF has good properties of uniqueness, reliability, and uniformity. Moreover, the resilient of MA-PUF against ML-attack is 15% better than a conventional Arbiter-PUF. The predictability of MA-PUF close to 65% could be achieved when combining with challenge permutation technique

Low-cost and portable automatic sheet cutter

Process automation is crucial to increase productivity, more efficient use of materials, better product quality, improved safety, etc. In small-medium enterprise (SME) businesses related to household retailing, one of the process automation needed is the measurement and cutting of the mat or sheet, made of rubber or polyvinyl chloride (PVC) materials. Most of the household retailers that selling the sheet, the process of measuring and cutting according to the customer’s requirements are manually performed using a measuring tape and scissors. These manual processes can cause inaccuracy in length, inefficient use of material, low productivity and reduce product quality. This paper presents a low cost and portable automatic sheet cutter using the Arduino development board, which is used to control the process of measuring and cutting the materials. The system uses a push-button where the user can set the required length and quantity of the sheet. Once the required information is set, the stepper motor rolls the sheet until the required length is satisfied. Subsequently, another stepper motor moves the cutter horizontally and cut the sheet. With the automatic sheet cutter, the material is cut with acceptable precision. The design of the automatic sheet cutter is low cost and portable which significantly suitable to be used by SME household retailers

Lightweight hardware fingerprinting solution using inherent memory in off-the-shelf commodity devices

An emerging technology known as Physical unclonable function (PUF) can provide a hardware root-of-trust in building the trusted computing system. PUF exploits the intrinsic process variations during the integrated circuit (IC) fabrication to generate a unique response. This unique response differs from one PUF to the other similar type of PUFs. Static random-access memory PUF (SRAM-PUF) is one of the memorybased PUFs in which the response is generated during the memory power-up process. Non-volatile memory (NVM) architecture like SRAM is available in off-the-shelf microcontroller devices. Exploiting the inherent SRAM as PUF could wide-spread the adoption of PUF. Therefore, in this study, we evaluate the suitability of inherent SRAM available in ATMega2560 microcontroller on Arduino platform as PUF that can provide a unique fingerprint. First, we analyze the start-up values (SUVs) of memory cells and select only the cells that show random values after the power-up process. Subsequently, we statistically analyze the characteristic of fifteen SRAM-PUFs which include uniqueness, reliability, and uniformity. Based on our findings, the SUVs of fifteen on-chip SRAMs achieve 42.64% uniqueness, 97.28% reliability, and 69.16% uniformity. Therefore, we concluded that the available SRAM in off-the-shelf commodity hardware has good quality to be used as PUF

Hybrid Mean Fuzzy Approach For Attention Detection

Statistics around the world showed that attention deficit significantly leads to road accidents. Hence, the growth of studies on attention deficit detection becoming more important. The studies obtained the waveform from electroencephalography (EEG) to identify the characteristic of attention. However, each individual has own unique characteristics to significantly shown the attention deficit. Thus, this research aim is to use the fuzzy approach to minimize the variability gap of the EEG signal between each individual. The research conducted the prior experiment to develop control parameter for training set of fuzzy by using two distinct stimulations to create two groups of attention sample i.e., attentive and inattentive. An approach of novel Hybrid Mean Fuzzy (HMF) was proposed in this research to detect attention deficit in EEG signal. It is the combination of simple averaging (Mean) and Fuzzy approaches for EEG analysis and classification. The results of using this method shows a significantly change in EEG signal which correlates to the attention detection. An Attention Degradation Scale (ADS) is successfully developed as the threshold value of EEG for attention detection. Therefore, the findings in this research can be a promising foundation on attention deficit detection in large application not only for reducing the road accidents

Modeling arbiter-PUF in NodeMCU ESP8266 using artificial neural network

A hardware fingerprinting primitive known as physical unclonable function (PUF) has a huge potential for secret-key cryptography and identification/authentication applications. The hardware fingerprint is manifested by the random and unique binary strings extracted from the integrated circuit (IC) which exist due to inherent process variations during its fabrication. PUF technology has a huge potential to be used for device identification and authentication in resource-constrained internet of things (IoT) applications such as wireless sensor networks (WSN). A secret computational model of PUF is suggested tobe stored in the verifier’s database as an alternative to challenge and response pairs (CRPs) to reduce area consumption. Therefore, in this paper, the design steps to build a PUF model in NodeMCU ESP8266 using an artificial neural network (ANN) are presented. Arbiter-PUF is used in our study and NodeMCU ESP8266 is chosen because it is suitable to be used as a sensor node or sink in WSN applications. ANN with a resilient back-propagation training algorithm is used as it can model the non-linearity with high accuracy. The results show that ANN can model the arbiter-PUF with approximately 99.5% prediction accuracy and the PUF model only consumes 309,889 bytes of memory space

Automatic generation of user-defined test algorithm description file for memory BIST implementation

Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking of the embedded memories on chips after the fabrication process. It can be used by implementing a standard testing algorithm available in the EDA tool library or a user-defined algorithm (UDA). This paper presents the development of software that automatically generates a description file of a UDA to be deployed for memory BIST circuit implementation using Tessent memory BIST software. It comprises the test setup and also the microprogram coding for each instruction to be executed when performing tests on embedded memories. The proposed automation software was tested by using March SR as the input algorithm and the results obtained from the simulations show that the output test patterns generated by the implemented memory BIST match the expected patterns and passed all the tests, which validated the correct functionality of the UDA description file generation. The proposed automation software also fast generation the UDA description file, which was completed in less than 500 ms

Secure lightweight obfuscated delay-based physical unclonable function design on FPGA

The internet of things (IoT) describes the network of physical objects equipped with sensors and other technologies to exchange data with other devices over the Internet. Due to its inherent flexibility, field-programmable gate array (FPGA) has become a viable platform for IoT development. However, various security threats such as FPGA bitstream cloning and intellectual property (IP) piracy have become a major concern for this device. Physical unclonable function (PUF) is a promising hardware finger-printing technology to solve the above problems. Several PUFs have been proposed, including the implementation of reconfigurable-XOR PUF (R-XOR PUF) and multi-PUF (MPUF) on the FPGA. However, these proposed PUFs have drawbacks, such as high delay imbalances caused by routing constraints. Therefore, in this study, we explore relative placement method to implement the symmetric routing in the obfuscated delay- based PUF on the FPGA board. The delay analysis result proves that our methodto implement the symmetric routing was successful. Therefore, our work has achieved good PUF quality with uniqueness of 48.75%, reliability of 99.99%, and uniformity of 52.5%. Moreover, by using the obfuscation method, which is an Arbiter-PUF combined with a random challenge permutation technique, we reduced the vulnerability of Arbiter-PUF against machine learning attacks to 44.50%

Network-on-chip non-preemptive test scheduling

Network-on-Chip (NoC) is an emerging design paradigm in complex system-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing scalability, and power dissipation, widespread interest in this novel paradigm is likely to grow. The reuse of on-chip network as test access mechanism has been proposed to handle the growing complexity for testing NoC-based systems. However, the NoC reuse is limited by the on-chip routing resources and various constraints. Therefore, efficient test scheduling methods are required to deliver feasible test time while meeting all the constraints. In this project, a new efficient test scheduling algorithm for NoCbased systems is proposed that can minimize the total test time. The proposed algorithm is more towards non-preemptive tests in terms of packet format by first considering the core that has biggest test time. The inherent parallelism within a NoC itself could be exploited to transport test data to IPs under test. The NoC switch and all interconnects are assumed fault free. This is to improve the efficiency by transporting test data on multiple paths and testing multiple NoC IPs concurrently. Experimental results for the ITC’02 SoC test benchmarks show that the nonpreemptive scheduling based on dedicated path able to give competitive results

Towards reliable and secure physical unclonable functions

Physical Unclonable Functions (PUFs) have emerged as a promising primitive that can be used to provide a hardware root of trust for integrated circuit (IC) applications. PUFs exploit the random intrinsic manufacturing process variations that map a set of challenges to a set of responses. The mapping of challenge-response pairs (CRPs) is unique and random to each PUF instance, which makes PUFs a very promising technology for robust security devices. PUFs have been proposed for lightweight IC identification and authentication, and cryptographic key generation. However, as CMOS technology scales down, device ageing becomes more pronounced and introduces reliability issues for PUF circuits. When PUFs undergo ageing, the response changes. As a consequence, the trustworthy identity of the ICs can be violated. The area overhead of an error correction code (ECC) in a PUF-based system needed to generate error-free cryptographic keys also increases. Furthermore, a PUF is physically unclonable but its function is susceptible to modelling attacks from machine learning (ML) techniques. Therefore, providing reliable and secure PUFs for lightweight applications is a major challenge. This thesis studies the reliability of PUFs for lightweight applications under ageing. It also considers the susceptibility of PUFs to ML-based attacks. This thesis presents three major contributions. The context of the first and second contributions is within the lightweight IC identification and authentication, and the third contribution is within the cryptographic key generation. The first contribution presents an analysis of the impact of ageing on PUF-based differential architectures. The simulation results demonstrate that a differential design technique to build a PUF can be a mechanism to mitigate the first-order dependencies of ageing such as the dutycycle and supply voltage. The second contribution proposes a challenge permutation technique to increase the complexity of the CRP mapping. The technique has been implemented on an Arbiter-PUF using a TSMC 65-nm technology. The simulation results show that using a challenge permutation technique can alter the output transition probability of Arbiter-PUF, resulting in the reduction of its predictability from 99% to 65%. The challenge permutation technique introduces no extra overhead as it can be implemented by routing obfuscation. Finally, the third contribution proposes a bit selection technique in a dual use of SRAM as a memory and PUF to mitigate the ageing impact and reduce the area overhead of the ECC. The results show that the proposed technique can effectively reduce the bit errors due to ageing and the area overhead of the ECC is reduced by about 6 times compared to that without bit selection

Dataset for: Towards Reliable and Secure Physical Unclonable Functions

Research data for the Ph.D. thesis titled: Towards Reliable and Secure Physical Unclonable Functions. Author: Mohd Syafiq Mispan. Year: 2018.</span